general description the ds4077 is an integrated voltage-controlled crystaloscillator (vcxo) module designed to provide reference clock generation in base stations, telecom/datacom, and wireless applications. the ds4077 is developed using a fundamental quartz crystal plus a unique integrated cir- cuit design. the internal fundamental quartz crystal determines the frequency of operation. custom frequen- cies are available. contact the factory for availability. the ds4077 is designed for use with applications requir- ing low phase noise and jitter. jitter performance of bet- ter than 0.8ps rms is achieved over the 12khz to 20mhz range. phase noise performance of better than -125dbc/hz at 1khz is achieved with this design. features ? 50mhz to 122.88mhz frequency ? 3.135v to 3.465v operation ? low jitter: < 0.8ps rms ? 69ppm absolute pull range (apr) ? output options: lvcmos output buffer lvds complementary output buffer ? minimum 110ppm tuning range (+25c) ? 14mm x 9mm x 3.06mm plastic lga package ds4077 50mhz to 122.88mhz vcxo ______________________________________________ maxim integrated products 1 n.c. n.c. n.c. n.c. lvcmos (lvdso+) v ss 1 9 8 7 6v dd 5 n.c. (lvdso-) vc ( ) lvds option transfer-molded plastic package lga top view 234 ds4077 pin configuration applications rev 3; 9/06 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range output type frequency (f nom ) (mhz) pin-package top mark ds4077l-dcn -40? to +85? lvcmos 54 9 lga ds4077l-dcn ds4077l-ddn -40? to +85? lvds 54 9 lga ds4077l-ddn ds4077l-ccn -40? to +85? lvcmos 61.44 9 lga ds4077l-ccn ds4077l-cdn -40? to +85? lvds 61.44 9 lga ds4077l-cdn ordering information continued at end of data sheet. clock-data recovery in telecom/datacomapplications data retiming reference clock generation in base stations and wireless applications block diagram x1 v dd lvcmosoutput varactor osc control lvcmos option shown here. crystal vc x2 ds4077 downloaded from: http:///
ds4077 50mhz to 122.88mhz vcxo 2 __________________________________________________ ___________________ absolute maximum ratings electrical characteristics (v dd = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (typical values at +25?, v dd = 3.3v, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. vc, v dd , lvcmos, lvdso+, lvdso- output ........-0.3v, +3.6v operating temperature range (noncondensing) ..............................................-40? to +85? junction temperature ......................................................+150? thermal resistance junction to ambient .................................................91.06?/w junction to case ......................................................44.51?/w storage temperature range .............................-55? to +125? soldering temperature (reflow, 2 passes max)....see ipc/jedec std-020 specification parameter symbol conditions min typ max units v dd operating supply range v dd 3.135 3.3 3.465 v f out 106.25mhz 20 30 v dd supply current i dd output open f out > 106.25mhz 25 35 ma frequency f out vc = 1.6v, v dd = 3.3v, t a = +25? (note 2) f nom ?ppm f nom f nom +8ppm mhz frequency vs. v dd sensitivity v dd ppm v dd = 3.3v ?% -3.5 +11.5 ppm frequency vs. load sensitivity loadpmm 10pf to 20pf (note 3) -1 ppm/pf frequency vs. temperature tempppm from +25? -20 +20 ppm vc voltage range vc range 0.3 1.60 2.8 v frequency tuning sensitivity vc sen 41 164 ppm/v tuning voltage bandwidth vc bw (note 3) 10 khz absolute pull range f tune vc = 0.3v to 2.8v (note 2) -69 +69 ppm vc input leakage i lcv vc = 0v to v dd -500 +500 na aging, first year ageppm -5 +5 ppm aging, years 0?0 t age total aging -10 +10 ppm lvds output output high voltage v ohlvdso (note 4) 1.475 v output low voltage v ollvdso (note 4) 0.925 v differential output voltage v odlvdso (note 4) 250 400 mv output common-mode variation v lvdsocom (note 4) 150 mv offset output voltage v offlvdso (note 4) 1.125 1.275 v differential output impedeance r olvdso (note 3) 80 140 output current i vsslvdso short ground 40 ma output current i lvdso short together (note 3) 12 ma output rise time (differential) t rlvdso 20% to 80% (note 3) 150 ps output fall time (differential) t flvdso 80% to 20% (note 3) 150 ps downloaded from: http:///
ds4077 50mhz to 122.88mhz vcxo ___________________________________________________ __________________ 3 electrical characteristics (continued) (v dd = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (typical values at +25?, v dd = 3.3v, unless otherwise noted.) (note 1) note 1: limits at -40? are guaranteed by design and not production tested. note 2: 10pf, lvcmos. note 3: guaranteed by design and not production tested. note 4: 100 differential load. parameter symbol conditions min typ max units lvcmos output output logic 0 v ol output current -450? 0 0.4 v output logic 1 v oh output current +450? v dd - 0.8v v dd v output rise time t r load condition: 10pf to ground; 10% to90% v dd (note 3) 2n s output fall time t f load condition: 10pf to ground; 90% to10% v dd (note 3) 2n s duty cycle d cyc load condition: 10pf, v dd / 2 (note 3) 40 60 % harmonics h v dd = 3.3v, t a = +25? (note 3) -18 -8 dbc/hz ssb phase noise and jitter, v dd = 3.3, t a = +25? (note 3) 10hz offset -70 100hz offset -100 1khz offset -125 10khz offset -145 100khz offset lvcmos -150 dbc/hz jitter (12khz to 20mhz) 0.8 ps rms pin description pin lvcmos lvds name function 1 1 vc vcxo control voltage 2, 5, 7, 8, 9 2, 7, 8, 9 n.c. no connection 3 3 v ss ground 4 lvcmos lvcmos output 6 6 v dd dc power 4, 5 lvdso+/lvdso- lvds positive and negative outputs downloaded from: http:///
ds4077 50mhz to 122.88mhz vcxo 4 __________________________________________________ ___________________ typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) frequency vs. temperature ds4077 toc01 temperature ( c) f out deviation (ppm) 60 40 20 0 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -40 80 f out = 77.76mhz vc = 1.55v lvcmos output frequency vs. load capacitance vs. vc ds4077 toc02 vc (v) f out deviation (ppm) 2.8 1.8 2.3 1.3 0.8 -50 -75 -100 125 100 7550 25 0 -25 150 -125 0.3 c l = 0pf c l = 20pf f out = 77.76mhz output frequency vs. supply voltage vs. vc ds4077 toc03 v dd (v) f out deviation from v dd = 3.3v (ppm) 3.410 3.465 3.355 3.190 3.245 3.300 -10 -15 1510 50 -5 20 -20 3.135 f out = 77.76mhz t a = +25 c vc = 0.3v vc = 2.8v vc = 1.6v downloaded from: http:///
ds4077 50mhz to 122.88mhz vcxo maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 5 2006 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. ordering information (continued) part temp range output type frequency (f nom ) (mhz) pin-package top mark DS4077L-ECN -40? to +85? lvcmos 74.17582 9 lga DS4077L-ECN ds4077l-edn -40? to +85? lvds 74.17582 9 lga ds4077l-edn ds4077l-fcn -40? to +85? lvcmos 74.25 9 lga ds4077l-fcn ds4077l-fdn -40? to +85? lvds 74.25 9 lga ds4077l-fdn ds4077l-acn -40? to +85? lvcmos 76.8 9 lga ds4077l-acn ds4077l-adn -40? to +85? lvds 76.8 9 lga ds4077l-adn ds4077l-0cn -40? to +85? lvcmos 77.76 9 lga ds4077l-0cn ds4077l-0dn -40? to +85? lvds 77.76 9 lga ds4077l-0dn ds4077l-gcn -40? to +85? lvcmos 106.25 9 lga ds4077l-gcn ds4077l-gdn -40? to +85? lvds 106.25 9 lga ds4077l-gdn ds4077l-bdn -40? to +85? lvds 122.88 9 lga ds4077l-bdn revision history rev 0; 8/05: initial release. rev 1; 12/05: added lvds option. rev 2; 6/06: changed device description/frequency range; changed jitter typical value from 1 to 0.8psrms; added new parts numbers to ordering information table; changed jitter range upper limits from80mhz to 20mhz. rev 3; 9/06: changed v dd ppm units from ppm/pf to ppm; added separate i dd parameter for parts with f out greater than 106.25mhz. package type package code document no. 9 lga l949a-1 21-0265 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . downloaded from: http:///
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